1. Field of the Invention
The present invention relates to a highly dense integrated circuit and, more particularly, to a integrated circuit which is suitable for a highly dense semiconductor memory.
2. Description of the Prior Art
According to the prior art, there is disclosed in Japanese Patent Laid-Open Publication No. 51-104276 a technique, in which two kinds of gate oxide film thicknesses and two kinds of gate region surface concentrations are combined for high integration of a semiconductor memory. In Japanese Patent Laid-Open Publication No. 50-119543, moreover, there is disclosed a concept, in which the channel length or diffusion layer spacing of the transistors of a memory array unit is further reduced by implanting ions of high concentration in the Si surface of the memory array unit thereby to increase the integration. However, in case the size of the circuit elements such as the transistors is reduced by those techniques, the withstand voltage of those circuit elements against dielectric breakdown has to be reduced. Therefore, it is necessary to reduce either the power source voltage to be fed to those circuit elements or the signal voltage to be generated by those circuit elements in accordance with the reduction in the size of the circuit elements.
In view of the usability for the user, on the other hand, it is desired that the voltage impressed from the outside (i.e., the voltage impressed upon the power source pin of the package of a memory LSI) be constant irrespective of the size of the transistors constructing the memory. It is, therefore, undesirable to reduce the externally impressed voltage. As a result, the conventional techniques thus far described have failed to realize such a highly integrated memory as can use a high external voltage. This fact is not limited to the memory but applies to other integrated circuit circuitry as well.